The present invention relates generally to the field of data communications, and more particularly, to the field of serial communications bus controllers and microcontrollers that incorporate the same.
CAN (Control Area Network) is an industry-standard, two-wire serial communications bus that is widely used in automotive and industrial control applications, as well as in medical devices, avionics, office automation equipment, consumer appliances, and many other products and applications. CAN controllers are currently available either as stand-alone devices adapted to interface with a microcontroller or as circuitry integrated into or modules embedded in a microcontroller chip. Since 1986, CAN users (software programmers) have developed numerous high-level CAN Application Layers (CALs) which extend the capabilities of the CAN while employing the CAN physical layer and the CAN frame format, and adhering to the CAN specification. CALs have heretofore been implemented primarily in software, with very little hardware CAL support. Consequently, CALs have heretofore required a great deal of host CPU intervention, thereby increasing the processing overhead and diminishing the performance of the host CPU.
Thus, there is a need in the art for a CAN hardware implementation of CAL functions normally implemented in software in order to offload these tasks from the host CPU to the CAN hardware, thereby enabling a great savings in host CPU processing resources and a commensurate improvement in host CPU performance. One of the most demanding and CPU resource-intensive CAL functions is message management, which entails the handling, storage, and processing of incoming CAL/CAN messages received over the CAN serial communications bus and/or outgoing CAL/CAN messages transmitted over the CAN serial communications bus. CAL protocols, such as DeviceNet, CANopen, and OSEK, deliver long messages distributed over many CAN frames, which methodology is sometimes referred to as xe2x80x9cfragmentedxe2x80x9d or xe2x80x9csegmentedxe2x80x9d messaging. The process of assembling such fragmented, multi-frame messages has heretofore required a great deal of host CPU intervention. In particular, CAL software running on the host CPU actively monitors and manages the buffering and processing of the message data, in order to facilitate the assembly of the message fragments or segments into complete messages.
Based on the above and foregoing, it can be appreciated that there presently exists a need in the art for a hardware implementation of CAL functions normally implemented in software in order to offload these tasks from the host CPU, thereby enabling a great savings in host CPU processing resources and a commensurate improvement in host CPU performance.
The assignee of the present invention has recently developed a new microcontroller product, designated xe2x80x9cXA-C3xe2x80x9d, that fulfills this need in the art. The XA-C3 is the newest member of the Philips XA (eXtended Architecture) family of high performance 16-bit single-chip microcontrollers. It is believed that the XA-C3 is the first chip that features hardware CAL support.
The XA-C3 is a CMOS 16-bit CAL/CAN 2.0B microcontroller that incorporates a number of different inventions, including the present invention. These inventions include novel techniques and hardware for filtering, buffering, handling, and processing CAL/CAN messages, including the automatic assembly of multi-frame fragmented messages with minimal CPU intervention, as well as for managing the storage and retrieval of the message data, and the memory resources utilized therefor.
The present invention relates to a power conservation scheme that enables one or more hardware components of the microcontroller, e.g., the CPU core, to remain in a sleep or idle mode while other hardware components, e.g., CAL/CAN hardware components, are active, e.g., automatically assembling a multi-frame, fragmented message.
The present invention encompasses a method for conserving power in a CAN microcontroller that includes a processor core and a CAN/CAL module that includes a plurality of sub-blocks that cooperatively function to process incoming CAL/CAN messages, which method includes the steps of placing the processor core in a power-reduction mode of operation (e.g., a sleep or idle mode of operation), placing the CAN/CAL module in a power-reduction mode of operation, and activating the CAN/CAL module to process an incoming CAL/CAN message (e.g., to perform automatic hardware assembly of a multi-frame, fragmented CAL/CAN message), thereby terminating the power-reduction mode of operation thereof, while the processor core is in its power-reduction mode of operation.
In a preferred embodiment, the method further includes the steps of generating a message-complete interrupt in response to completion of assembly of the multi-frame, fragmented CAL/CAN message, and activating the processor core in response to the message-complete interrupt. In a particular preferred embodiment, the method further includes the steps of repeating the step of placing the CAN/CAL module in a power-reduction mode of operation and the activating step, in seriatim, a plurality of times, while the processor core is in its power-reduction mode of operation.
In a present specific implementation, the step of placing the CAN/CAL module in a power-reduction mode operation is performed by a power or sleep control module contained within the CAN/CAL module, in the following manner. Particularly, first logic circuitry associated with each of the plurality of sub-blocks generates a respective first signal having a first logic level if that sub-block is currently active, and having a second logic level if that sub-block is not currently active. Second logic circuitry generates a second signal having a first logic level if any of the first signals are at the first logic level, and having a second logic level in response to all of the first signals having the second logic level. Third logic circuitry generates a third signal having a first logic level if the processor core is not idle, and having a second logic level if the processor core is idle. Fourth logic circuitry generates a fourth signal having a first logic level if an incoming message is being received, and having a second logic level if an incoming message is not being received. Fifth logic circuitry generates a clock disable signal in response to the second, third, and fourth signals all being at their respective second logic level. Sixth logic circuitry disables a clock applied to the CAN/CAL module in response to the clock disable signal to thereby place the CAN/CAL module in the power-reduction mode of operation.
In a present specific implementation, the step of placing the processor core in a power-reduction mode of operation is performed by a power or sleep control module contained within the CAN/CAL module, in the following manner. Particularly, a first logic portion of the power control module generates a clock disable signal having a first logic level if the processor core has pending interrupts, and having a second logic level if the processor core has no pending interrupts, and a second logic portion of the power control module disables a clock applied to the processor core in response to the clock disable signal, to thereby place the processor core in the power-reduction mode of operation.
The present invention, in another of its aspects, encompasses a method for conserving power in a CAN microcontroller that includes a processor core and a CAN/CAL module, which method includes the steps of placing the processor core in a power-reduction mode of operation (e.g., a sleep or idle mode of operation), while the CAN/CAL module is actively processing an incoming CAL/CAN message (e.g., to perform automatic hardware assembly of a multi-frame, fragmented CAL/CAN message), and terminating the power-reduction mode of operation in response to an interrupt.
In a preferred embodiment, the CAN/CAL module automatically assembles incoming, multi-frame, fragmented messages while the processor core remains in its power-reduction mode of operation, and the CAN/CAL module generates a message-complete interrupt in response to completion of assembly of the multi-frame, fragmented message, whereby the terminating step is executed in response to the message-complete interrupt.
In a present specific implementation, the step of placing the processor core in a power-reduction mode of operation is performed by a power or sleep control module contained within the CAN/CAL module, in the following manner. Particularly, a first logic portion of the power control module generates a clock disable signal having a first logic level if the processor core has pending interrupts, and having a second logic level if the processor core has no pending interrupts, and a second logic portion of the power control module disables a clock applied to the processor core in response to the clock disable signal, to thereby place the processor core in the power-reduction mode of operation.
In yet another of its aspects, the present invention encompasses a method for conserving power in a CAN microcontroller that includes a processor core and a CAN/CAL module, which method includes the steps of placing the entire CAN microcontroller, including both the processor core and the CAN/CAL module in a power-down mode of operation, detecting receipt of an incoming message, and activating the CAN/CAL module in response to the detecting step to process the incoming message (e.g., to perform automatic hardware assembly of a multi-frame, fragmented CAL/CAN message), thereby terminating the power-down mode of operation of the CAN/CAL module, without terminating the power-down mode of operation of the processor core.
In a preferred embodiment, the method further includes the step of placing the processor core in a power-reduction mode of operation (e.g., a sleep or idle mode of operation) in response to the detecting step. The processor core can be substantially instantaneously woken up when in the power-down mode of operation, and can be woken up over a prescribed wake-up period when in the power-down mode of operation.
In a specific implementation, the placing step is performed by determining whether the CAN/CAL module is ready to be placed into the power-down mode of operation, and stopping a main system clock in response to a determination that the CAN/CAL module is ready to be placed into the power-down mode of operation. Further, in the specific implementation, the method further includes the step of terminating the power-down mode of operation of the entire CAN microcontroller, including both the processor core and the CAN/CAL module, in response to an external interrupt or a system reset command.
In yet other aspects, the present invention encompasses a CAN microcontroller that implements any one or more of the above-discussed methods.